-
摘要: 為了降低硬件開銷，越來越多的加法器電路采用傳輸管邏輯來減少晶體管數量，同時導致閾值損失、性能降低等問題。本文通過對擺幅恢復邏輯與全加器電路的研究，提出一種基于擺幅恢復傳輸管邏輯（Swing restored pass transistor logic, SRPL）的全加器設計方案。該方案首先分析電路的閾值損失機理，結合晶體管傳輸高、低電平的特性，提出一種擺幅恢復傳輸管邏輯的設計方法；然后，采用對稱結構設計無延時偏差輸出的異或/同或電路，利用MOS管補償閾值損失的方式，實現異或/同或電路的全擺幅輸出；最后，將異或/同或電路融合于全加器結構，結合4T XOR求和電路與改進的傳輸門進位電路實現擺幅恢復的高性能全加器。在TSMC 65 nm工藝下，本文采用HSPICE仿真驗證所設計的邏輯功能，與文獻相比延時降低10.8%，功耗延時積（Power-delay product, PDP）減少13.5%以上。Abstract: The adder circuit is the core component of the high-performance system-on-chip (SoC). It is also important in image and voice encryption. The full adder circuit is a basic unit with a very high reuse rate among all the units. Therefore, the design of an adder with high energy efficiency is of great significance for the optimization of digital circuit systems. In recent years, numerous researchers have studied the design of advanced adder circuits, which are characterized by high speed and low power consumption. To reduce the hardware overhead, an increasing number of adder circuits utilize the transmission tube logic to reduce the number of transistors. However, this method also brings about several negative effects, such as threshold loss and performance degradation. In this paper, by studying the swing recovery logic and full adder circuit, we proposed a full adder design scheme based on swing restored pass-transistor logic (SRPL). First, the threshold loss mechanism of the circuit was analyzed, and the characteristics of the high-efficiency transmission of high-level and low-level transistors were considered; then the design method of the swing recovery transmission tube logic was developed. We used a symmetric structure to design an XOR/XNOR circuit without delay deviation output. The two-shot MOS tube was used to compensate the threshold loss to realize the full swing output of the XOR/XNOR circuit. Finally, we fused the designed XOR/XNOR circuit to the full adder structure and used the 4T XOR sum circuit and the improved transmission gate carry circuit to implement the high-performance full adder for swing recovery. In the TSMC 65 nm process, the logic function of our method was verified by HSPICE simulation. Compared with the conventional approach, the delay is reduced by 10.8%, and the power-delay product (PDP) is reduced by more than 13.5%. The design method of low delay and full swing output of the SRPL circuit can be further applied to the design of other logic circuits, further promoting the practical process of the SRPL circuit.
-
Key words:
- XOR/XNOR circuit /
- swing recovery /
- high-performance full adder /
- threshold loss /
- full swing
-
圖 1 3T XOR/XNOR電路和傳輸管傳輸狀態分析。（a）異或/同或電路；（b）NMOS高電平傳輸狀態；（c）PMOS低電平傳輸狀態
Figure 1. 3T XOR/XNOR circuit and the transition analysis by pass transistor: (a) XOR/XNOR circuit; (b) logic “1” transition by NMOS; (c) logic “0” transition by PMOS
圖 2 改進型異或/同或電路與RC模型。（a）改進型異或/同或電路；（b）AB=11 異或電路RC模型；（c）AB=00 同或電路RC模型
Figure 2. Improved XOR/XNOR circuit and RC model: (a) improved XOR/XNOR circuit; (b) RC model of XOR circuit for AB=11; (c) RC model of XNOR circuit for AB=00
圖 4 異或/同或電路輸出電平對比。（a） XOR；（b） XNOR
Figure 4. Comparison of XOR/XNOR circuit output levels: (a) XOR; (b) XNOR
圖 6 求和電路與進位電路。（a）基于傳輸門的4T XOR求和電路；（b）基于傳輸門的進位電路；（c）改進的傳輸門進位電路
Figure 6. Sum circuit and carry circuit: (a) 4T XOR sum circuit based on transmission gate; (b) carry circuit based on transmission gate; (c) improved carry circuit based on transmission gate
圖 9 擺幅恢復7T XOR/XNOR電路仿真結果。（a）仿真波形圖；（b）不同負載下PDP對比
Figure 9. Swing recovery of 7T XOR/XNOR circuit: (a) simulation waveform; (b) PDP results under different load conditions
圖 10 不同電壓與不同負載下全加器電路仿真結果。（a）不同電壓下全加器電路功耗對比；（b）不同電壓下全加器電路延時對比；（c）不同電壓下全加器電路PDP對比；（d）不同負載下全加器電路PDP對比
Figure 10. Simulation results of full adder circuit under different voltages and loads: (a) power results for different voltages; (b) delay results for different voltages; (c) PDP results for different voltages; (d) PDP results under different load conditions
表 1 擺幅恢復7T XOR/XNOR電路與相關文獻比較結果
Table 1. 7T XOR/XNOR circuit and comparison results of related literature
下載: 導出CSV
表 2 全加器電路與相關文獻比較結果
Table 2. Full adder circuit and related literature comparison results
Full Adder Numbers of Transistors Area/(17.78 μm2) Threshold loss Delay/ps Power/μW PDP/aJ Improvement PDP/% SERF[4] 10 0.80 YES 188.23 3.68 692.69 11.5 10T[5] 10 0.77 YES 173.62 3.24 562.53 28.1 CMOS[7] 28 1.66 NO 154.01 4.24 653.00 16.6 TGA[8] 20 1.64 NO 120.60 4.57 551.14 29.6 TFA[9] 16 1.23 NO 117.33 4.48 525.64 32.8 14T[21] 14 1.00 NO 194.75 4.02 782.90 0 DPL[22] 28 2.09 NO 125.81 4.61 580.00 25.9 CPL[24] 32 2.68 NO 112.52 5.85 658.24 16.0 Hybrid[25] 16 1.47 NO 116.35 4.65 541.03 30.9 Proposed 26 1.73 NO 100.40 4.53 454.81 41.9
下載: 導出CSV
www.77susu.com<span id="fpn9h"><noframes id="fpn9h"><span id="fpn9h"></span> <span id="fpn9h"><noframes id="fpn9h"> <th id="fpn9h"></th> <strike id="fpn9h"><noframes id="fpn9h"><strike id="fpn9h"></strike> <th id="fpn9h"><noframes id="fpn9h"> <span id="fpn9h"><video id="fpn9h"></video></span> <ruby id="fpn9h"></ruby> <strike id="fpn9h"><noframes id="fpn9h"><span id="fpn9h"></span> -
參考文獻
[1] Jitendra K S, Srinivasulu A, Singh B P. A new low-power full-adder cell for low voltage using CNTFETs // 2017 9th International Conference on Electronics, Computers and Artificial Intelligence (ECAI). Targoviste, 2017: 1 [2] Tirumalasetty V R, Machupalli M R. Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications. <italic>Int J Electron</italic>, 2019, 106(4): 521 doi: 10.1080/00207217.2018.1545256 [3] Mewada M, Zaveri M, Thakker R. Improving the performance of transmission gate and hybrid CMOS full adders in chain and tree structure architectures. <italic>Integration</italic>, 2019, 69: 381 doi: 10.1016/j.vlsi.2019.09.002 [4] Shalem R, John E, John L K. A novel low power energy recovery full adder cell // Proceedings 9th Great Lakes Symposium on VLSI. Ypsilanti, 1999: 380 [5] Dokania V, Verma R, Guduri M, et al. Design of 10t full adder cell for ultralow-power applications. <italic>Ain Shams Eng J</italic>, 2018, 9(4): 2363 doi: 10.1016/j.asej.2017.05.004 [6] Suman M, Samanta J, Chowdhury D, et al. Relative performance analysis of different CMOS full adder circuits. <italic>Int J Comput Appl</italic>, 2015, 114(6): 8 [7] Brzozowski I, Kos A. Designing of low-power data oriented adders. <italic>Microelectron J</italic>, 2014, 45(9): 1177 doi: 10.1016/j.mejo.2014.04.022 [8] Mehrabani Y S, Eshghi M. A symmetric, multi-threshold, high-speed and efficient-energy 1-bit full adder cell design using CNFET technology. <italic>Circuits Syst Signal Process</italic>, 2015, 34(3): 739 doi: 10.1007/s00034-014-9887-1 [9] Basireddy H R, Challa K, Nikoubin T. Hybrid logical effort for hybrid logic style full adders in multistage structures. <italic>IEEE Trans Very Large Scale Integr Syst</italic>, 2019, 27(5): 1138 doi: 10.1109/TVLSI.2018.2889833 [10] Mehrabani Y S, Eshghi M. Noise and process variation tolerant, low-power, high-speed, and low-energy full adders in CNFET technology. <italic>IEEE Trans Very Large Scale Integr Syst</italic>, 2016, 24(11): 3268 doi: 10.1109/TVLSI.2016.2540071 [11] Ahmadpour S S, Mosleh M, Heikalabad S R. A revolution in nanostructure designs by proposing a novel QCA full-adder based on optimized 3-input XOR. <italic>Physica B-Condensed Matter</italic>, 2018, 550: 383 doi: 10.1016/j.physb.2018.09.029 [12] Ramachandran S, Sanapala K. Ultra-low-voltage GDI-based hybrid full adder design for area and energy-efficient computing systems. <italic>IET Circuits Devices Syst</italic>, 2019, 13(4): 465 doi: 10.1049/iet-cds.2018.5559 [13] Ahmed R U, Saha P. Implementation topology of full adder cells. <italic>Procedia Comput Sci</italic>, 2019, 165: 676 doi: 10.1016/j.procs.2020.01.063 [14] Amini-Valashani M, Ayat M, Mirzakuchaki S. Design and analysis of a novel low-power and energy-efficient 18T hybrid full adder. <italic>Microelectron J</italic>, 2018, 74: 49 doi: 10.1016/j.mejo.2018.01.018 [15] Valashani M A, Mirzakuchaki S. A novel fast, low-power and high-performance XOR-XNOR cell // 2016 IEEE International Symposium on Circuits and Systems (ISCAS). Montreal, 2016: 694 [16] Malini P, Balaji G N, Boopathiraja K, et al. Design of swing dependent XOR-XNOR gates based hybrid full adder // 2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS). Coimbatore, 2019: 1164 [17] Kandpal J, Tomar A, Adhikari S, et al. Design of low power and high speed XOR/XNOR circuit using 90 nm CMOS technology // 2019 2nd International Conference on Innovations in Electronics, Signal Processing and Communication (IESC). Shillong, 2019: 221 [18] Kumar P, Sharma R K. Low voltage high performance hybrid full adder. <italic>Eng Sci Technol Int J</italic>, 2016, 19(1): 559 [19] Naseri H, Timarchi S. Low-power and fast full adder by exploring new XOR and XNOR gates. <italic>IEEE Trans Very Large Scale Integr </italic>(<italic>VLSI</italic>)<italic>Syst</italic>, 2018, 26(8): 1481 doi: 10.1109/TVLSI.2018.2820999 [20] Goel S, Kumar A, Bayoumi M A. Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style. <italic>IEEE Trans Very Large Scale Integr </italic>(<italic>VLSI</italic>)<italic>Syst</italic>, 2006, 14(12): 1309 doi: 10.1109/TVLSI.2006.887807 [21] Radhakrishnan D. Low-voltage low-power CMOS full adder. <italic>IEE Proc-Circuits</italic>,<italic>Devices Syst</italic>, 2001, 148(1): 19 doi: 10.1049/ip-cds:20010170 [22] Shanmugam Y, Mangalam H. Comparative analysis of design of low power full adder structures for deep sub-micron technology. <italic>Asian J Res Social Sci Humanities</italic>, 2017, 7(2): 141 [23] Chang C H, Gu J M, Zhang M Y. A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits. <italic>IEEE Trans Very Large Scale Integr </italic>(<italic>VLSI</italic>)<italic>Syst</italic>, 2005, 13(6): 686 doi: 10.1109/TVLSI.2005.848806 [24] Navi K, Maeen M, Foroutan V, et al. A novel low-power full-adder cell for low voltage. <italic>Integr VLSI J</italic>, 2009, 42(4): 457 doi: 10.1016/j.vlsi.2009.02.001 [25] Bhattacharyya P, Kundu B, Ghosh S, et al. Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit. <italic>IEEE Trans Very Large Scale Integr </italic>(<italic>VLSI</italic>)<italic>Syst</italic>, 2015, 23(10): 2001 doi: 10.1109/TVLSI.2014.2357057 -
點擊查看大圖
計量
- 文章訪問數: 1823
- HTML全文瀏覽量: 1245
- PDF下載量: 56
- 被引次數: 0
